教师名录

蒋 力 讲师

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办公室电话:34208232

办公地点:SEIEE-3-521

电子邮件:jiangli@cs.sjtu.edu.cn

实验室: 先进计算机体系结构实验室

  • 研究兴趣
  • 教育背景
  • 工作经验
  • 教授课程
  • 论文发表
  • 项目资助
  • 获奖信息
  • 学术服务

Computer Architecture with Emerging Technologies and Applications;

Computer Aided Design, Electrocial Design Automation; IC Design.

  • Ph.D. in Computer Science and Engineering, The Chinese University of Hong Kong (CUHK), 11/2010 – 10/2013
  • MPhil in Computer Science and Engineering, The Chinese University of Hong Kong (CUHK), 8/2008 – 7/2010
  • B.S. in Computer Science and Technology, Shanghai Jiao Tong University (SJTU), 9/2003 – 7/2007


  • Assistant Professor, Since 12/2013, Department of Computer Science and Engineering, Shanghai Jiaotong UniversityShanghai, China
  • Research Assistant, 9/2008 – 10/2013, CUhk REliable computing laboratory Hong Kong SAR
  • Visiting Scholar, 10/2012 – 1/2013, Duke University Durham, NC, US
  • Research Scientist, 5/2012 – 8/2012, Huawei Beijing Research Institute Beijing, China
  • Research Scientist, 4/2010 – 9/2010, CRDC, Cisco System Inc. Shanghai, China
  • CS427 Multicore Architecture and Parallel Programming (Fall)
  • CS339 Computer Networks (Spring)

Please refer to my google scholar citation: 

http://scholar.google.com/citations?hl=en&user=wCxFd8YAAAAJ


[J4]. Naifeng Jing, Li Jiang, Tao Zhang, Fengfeng Fan, Chao Li, Xiaoyao Liang, "Energy Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs," IEEE Transactions on Computers (TC), 2015.

[J3]. X. Zhang, H. Li, L. Jiang and Q. Xu, "A Low-cost High-efficient Test Scheme for Through Silicon Vias", accepted by IEEE Transactions on Very Large Scale Integration (VLSI) Systems(TVLSI), 2015.



[J2] L. Jiang, Q. Xu and B. Eklow. "On Effective Through-Silicon Via Repair for 3D-Stacked ICs". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), vol.32, no.4, pp.559 - 571, April, 2013

[J1] L. Jiang, Q. Xu, K. Chakrabarty and T. M. Mak. "Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint". IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (TVLSI), vol.20, no.9, pp. 1621–1633, 2011


[C12]. Naifeng Jing, Shuang Chen, Shunning Jiang, Li Jiang, Chao Li, Xiaoyao Liang, “Bank Stealing For Conflict Mitigation in GPGPU Register File,” International Symposium on Low Power Electronics and Design (ISLPED), July 2015.
[C11]. Yiqing Hua, Chao Li, Weichao Tang, Li Jiang, Xiaoyao Liang, “Building Fuel Powered Supercomputing Data Center at Low Cost,” International Conference on Supercomputing (ICS), June 2015.

[C10]. Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing and Li Jiang*, "Jump Test for Metallic CNTs in CNFET-Based SRAM", accepted for publish in Design Automation Conference, 2015

[C9]. Z. Sun, L. Jiang, Q. Xu, Z. Zhang, Z. Wang and X. Gu, "On Test Syndrome Merging for Reasoning-Based Board-Level Functional Fault Diagnosis", accepted for publication in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2015. (acceptance rate: 108/318 = 33.9%).

[C8] Z. Sun, L. Jiang, Q. Xu, Z. Zhang, Z.Wang and X. Gu. "AgentDiag: An Agent-Assisted Diagnostic Framework for Board-Level Functional Failures". to appear in Proc. IEEE International Test Conference (ITC), 2013

[C7] L. Jiang, Q. Xu, F. Ye, K. Chakrabarty and B. Eklow. "On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs". to appear in Proc. ACM/IEEE Design Automation Conference (DAC), 2013

[C6] L. Jiang, Q. Xu and B. Eklow. "On Effective TSV Repair for 3D-Stacked ICs". In Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 793-798, 2012 

[C5] Q. Xu, L. Jiang, H. Li and B. Eklow. "Yield Enhancement for 3D-Stacked ICs: Recent Advances and Challenges". In Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 731-737, 2012 (Invited) 

[C4] L. Jiang, R. Ye and Q. Xu. "Yield Enhancement for 3D-Stacked Memory by Redundancy Sharing across Dies". In Proc. IEEE/ACMInternational Conference on Computer-Aided Design (ICCAD), pp. 230–234, 2010 (Nominated for Best Paper Award)


[C3] L. Jiang, Y. Liu, L. Duan, Y. Xie and Q. Xu. "Modeling TSV Open Defects in 3D-Stacked DRAM". In Proc. IEEE International Test Conference (ITC), pp. 1–9, 2010 

[C2] L. Jiang, Q. Xu, K. Chakrabarty and T. M. Mak. "Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test-Pin-Count Constraint". In Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 191–196, 2009 


[C1] L. Jiang, L. Huang and Q. Xu. "Test Architecture Design and Optimization for Three-Dimensional SoCs". In Proc. IEEE/ACM Design, Automation, & Test in Europe (DATE), pp. 220-225, 2009 


[w2] L. Jiang and Q. Xu. "3D IC/TSV Probe Test with Adhesive Silicon Interposer". In 3D Test Workshop in International Test Conference (ITC), 2012


[w1] L. Jiang, Q. Xu and B. Eklow. "Yield Driven System Integration for 2.5D SoC". In Proc. Workshop 3D Integration in Design, Automation, & Test in Europe (DATE), 2012

[P1] L. Jiang,Q. Xu,H.Y. Li,G.Q. Xu,S.B. Su,X.L. Zhang. "A Test Interposer and Probe Card Design for 3D Pre-bond Test". pending patent , 2013

-Youth sailing program of excellence in science and technology, Science and technology commission of Shanghai, 2015, PI

-CCF-Tencent rhino bird innovation fund, CCF, China Computer Federation, 2014, PI

-National Key Laboratory Open Project, Inspur, 2014, PI


  • Youth sailing program of excellence in science and technology, 2015

  • IEEE TTTC Doctoral Thesis Award Semi-final, Asian Test Symposium, Best Thesis Award (Rank 1), Nov. 2014

  • CCF-Tecent "rhino bird" innovation award

  • Nominated for Best Research Award, The 10th ACM-HK Student Research and Career Day, Co-organized by ACM-HK and Microsoft Research Asia, November 19th, 2013
  • Postgraduate Studentships, The Chinese University of Hong Kong Since 2010
  • Nominated for Best Paper AwardIEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2010
  • Certificate of Merit for Excellent Teaching Assistant Department of CS&E, CUHK, Hongkong SAR 2010
  • Postgraduate Studentships, The Chinese University of Hong Kong 2008-2010
  • Outstanding graduate of colleges and universities in Shanghai, China 2007

TPC Member: Asian Test Symposium Conference (ATS) 2015

Reviewer: IEEE Transaction on CAD of Integrated Circuits and Systems (TCAD)
Reviewer: IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)
Reviewer: IEEE Transactions on Computer (TC)
External Expert Reviewer: ACM/IEEE Design Automation Conference (DAC)2013
Reviewer: Asian Test Symposium conference (ATS)2013

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