Faculty

Jiang Li Assistant Professor

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Office Telephone: +86-21-34208232

Office Address: SEIEE-3-521

Email: jiangli@cs.sjtu.edu.cn

Lab: The China Ministry of Education (MOE) - Microsoft Key Laboratory of Intelligent Computing and System; Advanced Computer Architecture Laboratory

  • Research
  • Education
  • Work Experience
  • Teaching Assignment
  • Publications
  • Project Fund
  • Awards
  • Academic Service
1. Computer Design for Emerging Technologies (Neuromorphic Computing) and Applications (Deep Learning)

2. Fault Tolerant Computing

3. Heterogeneous Acceleration


-Ph.D. in Computer Science and Engineering, 11/2010 – 10/2013, The Chinese University of Hong Kong (CUHK)
-MPhil in Computer Science and Engineering, 8/2008 – 7/2010, The Chinese University of Hong Kong (CUHK)
-B.S. in Computer Science and Technology 9/2003 – 7/2007, Shanghai Jiao Tong University (SJTU)
-Research Assistant, 8/2008 - 10/2013, CUhk REliable computing laboratory Hong Kong SAR
-Visiting Scholar, 10/2012 – 1/2013, Duke University Durham, NC, US
-Internship, 5/2012 – 8/2012, Huawei Beijing Research Institute Beijing, China
-Internship, 4/2010 – 9/2010, CRDC, Cisco System Inc. Shanghai, China

CS427 Multicore Architecture and Parallel Programming (2014-2016)

CS339 Computer Networks (2014-2016)

CS308 Compiler Principles

CS222 Algorithm Design and Analysis (2015-2016)

Journal Publication: 

[TCAD’17] L. Jiang, T. Li, N. Jing, N. Kim, M. Guo and X. Liang, “CNFET-based High Throughput SIMD Architecture”. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), 2017 (SCI, CCF-A)

[TCAD’16] T. Li, F. Xie, X. Liang, Q. Xu, K. Chakrabarty, N. Jing and L. Jiang*, "A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs”. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), vol.35, no.7, pp. 1192 - 1205, 2016 (SCI, CCF-A)

[TVLSI’16] N. Jing, S. Jiang, S. Chen, J. Zhang, L. Jiang, C. Li, X. Liang, "Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol.PP, no.99, pp.1-14, 2016 (SCI, CCF-B)

[TC’16] N. Jing, L. Jiang, T. Zhang, F. Fan, C. Li and X. Liang, "Energy Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs". IEEE Transactions on Computers (TC), vol.65, no.1, pp.1-1, 2016 (SCI,CCF-A) 

[TVLSI’15] X. Zhang, H. Li, L. Jiang and Q. Xu, "A Low-cost High-efficient Test Scheme for Through Silicon Vias". accepted by IEEE Transactions on Very Large Scale Integration (VLSI) Systems(TVLSI), 2015 (SCI, CCF-B)

[TCAD’13] L. Jiang, Q. Xu and B. Eklow, "On Effective Through-Silicon Via Repair for 3D-Stacked ICs". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), vol.32, no.4, pp.559 - 571, April, 2013 (SCI, CCF-A)

[TVLSI’11] L. Jiang, Q. Xu, K. Chakrabarty and T. M. Mak., "Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint". IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (TVLSI), vol.20, no.9, pp. 1621_1633, 2011 (SCI, CCF-B) 

Conference Publication: 

[DAC’17]. Chengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao Liang and Li Jiang*, “On Quality Trade-off Control for Approximate Computing using Iterative Training”, accepted by ACM/IEEE Design Automation Conference (DAC), June. 2017

[DAC’17]. Tianjian Li, Xiangyu Bi, Naifeng Jing, Yu Wang, Xiaoyao Liang and Li Jiang*, “Sneak-path based Test and Diagnosis for 1R RRAM Crossbar using Voltage Bias Technique”, accepted by ACM/IEEE Design Automation Conference (DAC), June. 2017

[DATE’17]. Lerong Chen, Jiawen Li, Yiran Chen, Qiuping Deng, Jiyuan Shen, Xiaoyao Liang and Li Jiang*, "Learning Variations and Defects: a Neural-network Retraining Method for Fault Tolerance in the RRAM Crossbar”, accepted by ACM/IEEE Design Automation & Test in Europe Conference and Exhibition, April. 2017 (CCF-B)

[DATE’17]. Tianjian Li, Yan Han, Xiaoyao Liang, Hsien-Hsin S. Lee and Li Jiang*, "Fault Clustering Technique for 3D Memory BISR”, accepted by ACM/IEEE Design Automation & Test in Europe Conference and Exhibition, April. 2017 (CCF-B)

[ITC’16]. T. Li, L. Jiang*, X. Liang, Q. Xu and K. Chakrabarty, "Defect Tolerance for CNFET-based SRAMs", IEEE International Test Conference, paper 4.1, Nov. 2016 (CCF-B)

[ICCD’16]. T. Li, Li Jiang*, N. Jing, N. S. Kim and X. Liang, “CNFET-Based High Throughput Register File Architecture”, accepted by IEEE International Conference on Computer Design, pp. 662-669, Oct. 2016 (CCF-B)

[MICRO’16]. N. Jing,J. Wang, F. Fan, W. Yu, L. Jiang, C. Li and X. Liang, "Cache-Emulated Register File: An Integrated On-Chip Memory Architecture for High Performance GPGPUs". accepted by ACM/IEEE International Symposium on Microarchitecture, 2016 (CCF-A)

[ICCD’15]. L. Jiang, X. Huang, H. Xie, Q. Xu, C. Li, X. Liang and H. Li, "A Novel TSV Probing Technique with Adhesive Test Interposer", International Conference on Computer Design, pp. 597 - 604, Oct. 2015 (CCF-B) 

[ITC’15]. L. Jiang, P. Pang, N. Jing, S. K. Lim, X. Liang and Q. Xu, "On Diagnosable and Tunable 3D Clock Network Design for Lifetime Reliability Enhancement", International Test Conference, paper 17.1, Oct. 2015 (CCF-B)

[ITC’15]. L. Jiang, and Q. Xu, "Yield and Reliability Enhancement for 3D ICs", International Test Conference, paper DDC.3, Oct. 2015 (CCF-B)

[NOCS’15]. L. Jiang, and Q. Xu, "Fault-tolerant 3D-SoCs: Recent advances and challengs", accepted by Network-on-chip Symposium, Sep. 2015 (CCF-C)

[IEEE-SOCC’15]. T. Li, H. Chen, W. Qian, X. Liang, and L. Jiang*, "On Microarchitectural Modeling for CNFET-based Circuits", IEEE System On Chip Conference, Sep. 2015

[IEEE-SOCC’15]. C. Wang, L. Jiang*, T. Li, X. Liang, W. Qian, "Timing-Driven Placement for Carbon Nanotube Circuits", IEEE System On Chip Conference, Sep. 2015

[ISLPED’15]. N. Jing, S. Chen, S. Jiang, L. Jiang, C. Li, X. Liang, “Bank Stealing For Conflict Mitigation in GPGPU Register File,” International Symposium on Low Power Electronics and Design, pp. 55-60, July 2015 (CCF-B)

[ICS’15]. Y. Hua, C. Li, W. Tang, L. Jiang, Xiaoyao Liang, “Building Fuel Powered Supercomputing Data Center at Low Cost,” International Conference on Supercomputing, pp. 241-250, June 2015 (CCF-B)

[DAC’15] F. Xie, X. Liang, Q. Xu, K. Chakrabarty, N. Jing and L. Jiang*, "Jump Test for Metallic CNTs in CNFET-Based SRAM". Design Automation Conference, pp. 1-6, 2015 (CCF-B)

[ASP-DAC’13] Z. Sun, L. Jiang, Q. Xu, Z. Zhang, Z. Wang and X. Gu, "On Test Syndrome Merging for ReasoningBased Board-Level Functional Fault Diagnosis". Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 737 - 742, 2013 (Cooperated with Huawei) (CCF-C)

[ITC’13] Z. Sun, L. Jiang, Q. Xu, Z. Zhang, Z. Wang and X. Gu, "AgentDiag: An Agent-Assisted Diagnostic Framework for Board-Level Functional Failures". IEEE International Test Conference (ITC), paper 11.2, 2013 (Cooperated with Huawei) (CCF-C)

[DAC’13] L. Jiang, Q. Xu, F. Ye, K. Chakrabarty and B. Eklow, "On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs". Proc. ACM/IEEE Design Automation Conference, pp. 1 - 6, 2013 (CCF-B)

[DATE’12] L. Jiang, Q. Xu and B. Eklow, "On Effective TSV Repair for 3D-Stacked ICs". In Proc. Design, Automation & Test in Europe Conference & Exhibition, pp. 793-798, 2012(CCF-B)

[ASP-DAC’12] Q. Xu, L. Jiang, H. Li and B. Eklow, "Yield Enhancement for 3D-Stacked ICs: Recent Advances and Challenges". In Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 731-737, 2012 (Invited)(CCF-C)

[ICCAD’10] L. Jiang, R. Ye and Q. Xu, "Yield Enhancement for 3D-Stacked Memory by Redundancy Sharing across Dies". In Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 230 - 234, 2010 (Nominated for Best Paper Award)(CCF-B)

[ITC’10] L. Jiang, Y. Liu, L. Duan, Y. Xie and Q. Xu, "Modeling TSV Open Defects in 3D-Stacked DRAM". In Proc. IEEE International Test Conference, pp. 1 - 9, 2010(CCF-B)

[ICCAD’09] L. Jiang, Q. Xu, K. Chakrabarty and T. M. Mak, "Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test-Pin-Count Constraint". In Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 191 - 196, 2009(CCF-B)

[DATE’09] L. Jiang , L. Huang and Q. Xu, "Test Architecture Design and Optimization for Three-Dimensional SoCs". In Proc. IEEE/ACM Design, Automation, & Test in Europe, pp. 220-225, 2009(CCF-B)


- FPGA-based Acceleration for Deep Learning Algorithms (ZTE)

- Eye tracking technology and new human-computer interaction (Recruiting Self Motivated Students) (Funded by Tecent)

- DNN-based object recognition in the harbor! (Industry Fund)

- DNN-aided diagnosis in medical application! (Industry Fund)

- Neuro Processing Unit for approximate computing: architecture and applications! (Funded by NSFC)

- Computer Architecture for Carbon-Nanotube FETs! (Funded  by Shanghai Science and Technology Committee)

-Finalist on 10th ACM-HK Student Best Research Award, HKUST HongKong SAR 2013
-Postgraduate Studentships, CUHK Hong Kong SAR 2010-2013
-Nominated for Best Paper Award, IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2010
-Certificate of Merit for Excellent Teaching Assistant Department of CS&E, CUHK Hongkong SAR 2010
-Postgraduate Studentships, CUHK Hong Kong SAR 2008-2010
-Outstanding graduate of colleges and universities in Shanghai, Shanghai,China 2007

TPC Member: Design Automation and Test in Europe Conference (DATE), 2017; Asian Test Symposium (ATS), 2014 

Reviewer: IEEE Transaction on CAD of Integrated Circuits and Systems (TCAD)

Reviewer: IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)

Reviewer: IEEE Transactions on Computer (TC)

External Expert Reviewer: ACM/IEEE Design Automation Conference (DAC)2013

Reviewer: Asian Test Symposium conference (ATS)2013

TPC Member, The 2015 3D-Test workshop

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